EDN

In-System Silicon Validation and Debug

This is the third and final article in a series about silicon validation. Part 1 described the silicon validation problem and the basic requirements of an effective and scalable solution. Part 2 ...
Business Wire

ProDesign Joins Synopsys in-Sync Program to Enable Unified ASIC Prototyping and Verification; Common ASIC Flow Optimized for Customer Productivity

SAN JOSE, Calif.--(BUSINESS WIRE)--April 4, 2005--ProDesign USA, a leading supplier of high-speed FPGA-based ASIC verification platforms, today announced that it has joined the Synopsys in-Sync(R) ...
Semiconductor Engineering

Case Study—RF ASIC Validation Of A Satellite Transceiver

ASIC validation in the RF world comes with its own set of hurdles and challenges, with high-quality lab equipment, experience and know-how essential. A recently completed RF sub-system validation at ...
EDN

Demonstrating ASIC IP performance and quality demands an FPGA-neutral design flow

Companies designing new system-on-chip (SoC) products are subject to ongoing market pressure to do more with less and achieve higher returns. The result is shrinking engineering teams, reduced design ...