Cupertino, Calif. How do you design a 10-million-gate chip on a tight schedule? Not one gate at a time. Simon Bloch is president and CEO of Aristo Technology Inc., Cupertino, Calif. The recent winner ...

Editor's Note: In Part 3 of this series, consultant and ASIC designer Tom Moxon covered several RTL and logic synthesis design flows. In this installment of the series, he'll describe new physical ...

As semiconductor technology pushes the boundaries of scale and complexity, traditional VLSI physical design methodologies are struggling to keep pace. The rise of Artificial Intelligence (AI), ...

Physical design for reuse remains stuck at the hard macro, which prevents intellectual property from being optimized to the target design or easily migrated to the next process generation. By contrast ...