EDN

IMEC benchmarks FinFET superiority

LONDON – The IMEC researchinstitute has compared one planar and two FinFET technologies to see how theyperform against scaling and process variability. The benchmark circuits weresix-transistor SRAM ...
EDN

1-Transistor SRAM Cell Scales to FinFET Technology Node

Zeno’s one-transistor Bi-SRAM uses a single transistor and is ~5× smaller than a conventional SRAM — which uses six-transistor bitcells (6T-SRAM) — at the same technology node One way to look at a ...
Semiconductor Engineering

Stress-Related Local Layout Effects In FinFET Technology And Device Design Sensitivity

“Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity ...
Electronic Design

FinFETs Create Smallest SRAM Cell Ever

At 0.128 µm2, a new SRAM cell using fin-shaped FETs (FinFETs) is the smallest such cell ever developed, according to Toshiba Corp, IBM, and AMD. At 0.128 µm 2, a new SRAM cell using fin-shaped FETs ...
Semiconductor Engineering

Scaling The Lowly SRAM

Chipmakers face a multitude of challenges at the 20nm logic node and beyond, including the task of cramming more functions on the same chip without compromising on power and performance. There is one ...
Design-Reuse

Synopsys' Custom Compiler Certified for TSMC 10-nm and 7-nm FinFET Process Nodes

MOUNTAIN VIEW, Calif., Mar. 30, 2016 – Synopsys, Inc. (Nasdaq: SNPS) today announced that the company's new Custom Compiler™ tool (see today's news release) has been certified by TSMC for 10-nanometer ...
Electronic Design

FinFETs Herald A Seismic Shift In Semiconductor Technology

When making the transition from planar devices to FinFETs, IP design challenges arise that require education and experience when dealing with the complexities. Since the inception of the ...