EDN

Focus is on the best ASIC design flow

System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based system-on-a-chip ASIC design. The immediate attraction of SoPC is that, like a breadboard, the ...
EDN

Managing Data Flow in SoC and ReConfigurable Platform-Based Silicon Solutions

System-on-Chip (SoC) device and reconfigurable platform-based silicon solutions combine embedded hardware and software with a staggeringly high level of complexity. While hardware and software ...
Semiconductor Engineering

C-Based SoC Design Flow And EDA Tools

This paper examines the achievements and future of SoC design methodology and design flow from the viewpoints of an in- house EDA team of an ASIC and system vendor. We initially discuss the problems ...
FOX40 News

Baum’s Power Analysis Suite is Adopted for ASICLAND SoC Design Flow

PowerBaum is now offered through ASICLAND's solution SoC model, in which ASICLAND is involved in customers' product development process early on. Supporting power analysis service from the early ...
Electronic Design

Flow Software Cuts ASIC Modelling Time

It is important to model an SoC well in advance to avoid costly over design or insufficient performance and to create a hardware emulation on which representative end user applications can be run. It ...
Business Wire

ProDesign Joins Synopsys in-Sync Program to Enable Unified ASIC Prototyping and Verification; Common ASIC Flow Optimized for Customer Productivity

SAN JOSE, Calif.--(BUSINESS WIRE)--April 4, 2005--ProDesign USA, a leading supplier of high-speed FPGA-based ASIC verification platforms, today announced that it has joined the Synopsys in-Sync(R) ...
Semiconductor Engineering

Add Security And Supply Chain Trust To Your ASIC Or SoC with eFPGAs

Before Covid-induced supply chain issues affected semiconductor availability and lead times, concerns about counterfeit parts and trusted supply chains were becoming the subject of many articles and ...
Business Wire

Aldec Launches HES-DVM Proto ‘Cloud Edition’ - Giving Engineers Easier Access to FPGA-based ASIC & SoC Prototyping

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has launched HES-DVM Proto Cloud Edition (CE).
Electronic Design

Custom Blocks Fortify eFPGAs While Shrinking ASIC/SoC Die Size

For more than three decades, system-level designers have employed FPGAs for multitude of reasons, but the two main factors are performance and flexibility. Many tasks executed in software running on a ...
Embedded

Embedded.com Tech Focus Newsletter (1-27-14): Dealing with embedded SoC design challenges

For hands-on stories of how embedded hardware developers are solving difficult SoC, chip and board design problems, two excellent venues are Embedded.com and this week’s 2014 Designcon meeting of ...
Design-Reuse

Faraday Announces Successful Implementation of 533 MHz ARM(R) Compliant Core -- FA626 in 130nm SoC ASIC

HSINCHU, Taiwan and SUNNYVALE -- May 13, 2008 -- Faraday Technology (TAIEX: 3035), a leading ASIC and IP provider, today announced that it has successfully integrated a hardened 533Mhz ARM(R) ...