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4. The schematic circuit diagram (on the left) and cross-sectional structure (on the right) of adynamic random access memory (DRAM) unit cell is shown below.Word lineAccesstransistorword lineto groundbit linenBit lineStoragecapacitor(a). If the storage capacitor is implemented using a MOS capacitor (as shown in the cross-sectional structure above) of the smallest possible size according to the λ-layout designrules for an n-channel MOS transistor, sketch the layout of the DRAM cell.(b). Using the
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